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Diplomarbeit 2004 (DA04): Arbeits-Archiv
 
DA Bar 04/1 - Microwave frequency synthesizer with direct digital synthesis (DDS)
Studierende: Serge Niebergall, niebeser

Betreuer: Werner Baumberger, bauw

The aim of this work was to develop and to test the functionality and performance of a new kind of a phase-locked loop (PLL). The speciality of this PLL: a fractional divider (DDS-chip) replaces the integer divider (Prescaler)in the feedback loop. Several advantages are expected with this new design considering the classical design. During this work I designed PCB-Layouts with the program Protel DXP for the components of the Synthesizer working at a maximum frequency of 400 MHz. These were improved and enhanced during function tests. At the end the working PLL (including DDS) was submit to different tests. The second aim of this work, a PLL with a output Frequency above 3 GHz, was not accomplished because of lack of time. The main problems of this work:

? Understanding the functionality and the co-operation of the PLL components. ? Developing, assembling and testing the components. ? Putting the PLL into operation ? Determination of the advantages and disadvantages of the DDS in the new environment.

The PLL with the DDS-chip in the feedback loop works as expected. There are some restrictions according to the slope of the square signal at the input of the phase detector and the selection of the scale value of the DDS, though. This work builds a good base for a further design of a high frequency PLL above 3GHz.

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