In recent years, field-programmable gate arrays (FPGA's) have becom key components in implementing high performance digital signal processing(DSP) systems.

The company Stettbacher Signal Processing AG provided us a digital 3-band equalizer, on the base of an FPGA (Virtex-II). The main goal was to improve the filter design, which structure was parallel implemented. Because of that, the FPGA needed 20 multiplier out of 40. First of all we had to optimize them in a sequential structure. After that we developed a 5-band system with a graphic user interface, which is running on a Linux PC. In Addition we used a 128 Point FFT to measure the band deflexion. To accomplish these tasks we broke down our project into 6 more or less independent parts, which consisted of:

• Equalizer: development of a 5 band equalizer with a sequential filter design
• FFT: implementation of a 1024 Point FFT, by which we could use 128 Points
• Graphical User Interface: an easy control unit for the Virtex-II
• Effects: artificial Reverberation and Noiscutt
• USB: interface between the FPGA Virtex-II and the PC

The equalizer was realized with the Virtex-II Reference Board from Insight. The Virtex-II has an highly device complexity and consists of 40 18*18 multipliers and over 10'000 Flip-Flops. The FTDI Chip FT245BM provided the USB interface, which comes with a 4-Wire handshake to communicate with the FPGA.\\ To develop our software we needed a whole set of programs. We will only introduce the most important ones:

• Xilinx System Generator: for the optimization and simulation of the sequential filters
• ISE: VHDL programming platform
• KDevelop:Linux programming environment